1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise highly capacitive gate structures including a high-k gate dielectric.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm.
In such advanced transistor elements, reliability and lifetime thus significantly depends on short channel effects, i.e., impact ionization and hot carrier injection into the gate dielectric material, while gate leakage currents may also significantly increase when using silicon-based gate dielectrics of a reduced thickness. For example, since device dimensions have been scaled down more rapidly compared to the supply voltages, the resulting electrical field strengths in the gate dielectric material have significantly increased, while at the same time the threshold voltage of the transistors, i.e., the voltage at which a conductive channel forms in the channel region, has been reduced in order to improve drive current and switching speed of sophisticated transistors. Consequently, the quality of the gate dielectric material may strongly influence the transistor behavior, while at the same time a high stability of the threshold voltage of the transistor may be required over the rated lifetime in order to fulfill the required device qualifications. Upon further scaling the critical dimensions of transistor elements, a further long known effect may increasingly play an important role for CMOS devices when threshold voltages and, to a less pronounced degree, also the supply voltages are steadily reduced. It has been observed in the late '60s that the application of voltage, such as a negative voltage, in combination with thermal stress to the gate electrode of MOS transistor may result in a shift of the threshold voltage. This effect, also referred to as “bias temperature instability or injection” is mainly present in PMOS transistors and was not considered particularly relevant for semiconductor devices in the following years due to the low influence on the overall device performance of devices, in particular as NMOS devices have increasingly been developed. This situation changed with the introduction of complex CMOS devices including high performance logic circuits in which millions of signal nodes with PMOS and NMOS transistors are typically provided. In these devices, the threshold voltage and the supply voltage have constantly been reduced, while, on the other hand, the electric field strengths across the gate dielectrics have increased. Under such conditions, a change of the threshold voltage may have an even higher impact since transistor operation variability may increase due to the relatively higher influence of a shift of the threshold voltage. Furthermore, the operating states of the transistors resulting in the application of voltage pulses, such as negative and positive voltages, to the gate electrode of PMOS transistors may depend on the signal path considered and the overall operational conditions, thereby resulting in substantially non-predictable threshold shifts within the lifetime of the device. For example, a shift of the threshold voltage over the accumulated operating time may finally lead to a violation of time specifications of the device, which may not allow a further use of the device despite the fact that no other major failure has occurred.
Generally, this effect is also associated with the quality of the gate dielectric material and in particular with the quality of the interface between the semiconductor material in the channel region and the gate dielectric material. In this case, upon certain operational conditions, such as elevated temperatures and other stress conditions, a charge trap is created in the vicinity of the interface, wherein, in particular, holes may be trapped, thereby resulting in a significant shift of threshold voltage by localized positive interface states and the additionally trapped charges. In NMOS transistors, this effect may be significantly less pronounced since the interface states and the fixed charges are of opposite polarity, thereby resulting in lower performance degradation.
In view of reducing short channel effects and undesired gate leakage currents, the replacing of silicon dioxide or at least a portion thereof as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide-based material. It has, thus, been suggested to replace silicon dioxide-based materials, at least partially, with materials of an increased dielectric constant, such as hafnium-based dielectric materials, zirconium oxide and the like. In some conventional approaches a “conventional” gate dielectric material, such as silicon dioxide, silicon oxynitride and the like, may be formed on the semiconductor material of the channel region, followed by the high-k dielectric material, which may then be capped by an appropriate conductive material, such as titanium nitride and the like, in combination with an appropriate metal species, such as lanthanum, aluminum and the like, in order to adjust the work function as may be required for N-channel transistors and P-channel transistors, respectively. To this end, in some conventional approaches, an additional adaptation of the electronic configuration of the semiconductor material in the channel region with respect to the work function may be required, which may be accomplished by providing an appropriate semiconductor material in order to obtain the required band gap offset. For this purpose, in the P-channel transistor, a silicon/germanium semiconductor mixture or alloy may be provided with a specific thickness and germanium concentration in order to obtain the required band gap offset and thus a desired threshold voltage of the P-channel transistor. Typically, a corresponding specifically designed semiconductor material, such as the silicon/germanium alloy and the like, is provided by an epitaxial growth technique at an early manufacturing stage prior to forming the gate dielectric material. Although the usage of high-k gate dielectric materials may enable a further scaling of the channel length of critical transistor elements, it turns out, however, that, in particular, significant threshold voltage instabilities in P-channel transistors may cause significant yield losses, which is believed to be caused by the complex material system of the threshold adjusting semiconductor alloy in combination with the high-k gate dielectric material, as will be explained with reference to FIGS. 1a-1g. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, above which is formed a silicon-based semiconductor material 102 having an appropriate thickness for forming therein and thereabove transistor elements. An isolation structure 102C is formed in the semiconductor layer 102, thereby laterally delineating active regions 102A, 102B. In this context, an active region is to be understood as a semiconductor material in which an appropriate dopant profile is to be created in order to form PN junctions for one or more transistor elements. In the example shown, the active region 102A corresponds to a P-channel transistor while the active region 102B represents an N-channel transistor. That is, the active regions 102A, 102B may comprise, in the manufacturing stage shown, an appropriate basic dopant concentration in order to determine the conductivity of a P-channel transistor and an N-channel transistor, respectively. Moreover, a mask layer 103 is formed on the active regions 102A, 102B, for instance in the form of a silicon dioxide material and the like. Furthermore, an etch mask 104 is provided such that the active region 102B is covered, while the active region 102A, i.e., the mask layer 103 formed thereon, is exposed to an etch ambient 105.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following conventional process strategies. First, the isolation structure 102C is formed on the basis of well-established lithography, etch, deposition, planarization and anneal techniques, in which, for instance, a trench is formed in the semiconductor layer 102, which is subsequently filled with an appropriate insulating material, such as silicon dioxide, silicon nitride and the like. After removing any excess material and planarizing the surface topography, the process is typically continued by performing a plurality of implantation sequences using an appropriate masking regime in order to introduce the required dopant species for generating the basic dopant concentration in the active regions 102A, 102B. After activating the dopant species and re-crystallizing implantation-induced damage, the further processing is continued by forming the mask layer 103 on the basis of an oxidation process and the like, followed by the deposition of a mask material, such as a resist material, that is subsequently patterned into the mask 104 by well-established lithography techniques. Next, the etch process 105 is performed, for instance using a wet chemical etch recipe based on, for instance, hydrofluoric acid (HF), which may remove silicon dioxide material selectively with respect to silicon material.
FIG. 1b schematically illustrates the semiconductor device 100 after the above-described process sequence and after the removal of the etch mask 104 (FIG. 1a). Furthermore, in this manufacturing stage, additional cleaning processes may be performed in order to prepare the surface of the active region 102A for the deposition of a silicon/germanium alloy as required for adapting the threshold voltage in combination with a high-k dielectric material and a gate electrode material still to be formed.
FIG. 1c schematically illustrates the semiconductor device 100 during a selective epitaxial growth process 108 in which process parameters are selected in accordance with well-established recipes such that material deposition is substantially restricted to the exposed active region 102A, while a material deposition on dielectric surface areas, such as the isolation structure 102C and the mask layer 103, is strongly suppressed. Thus, during the selective epitaxial growth process 108 a silicon/germanium alloy 109 may, therefore, be selectively formed on the active region 102A, wherein the material composition as well as the layer thickness have a strong influence on the finally obtained threshold voltage of a P-channel transistor still to be formed in and above the active region 102A. For example, a target thickness of the material 109 may be approximately 10-50 nm with a germanium concentration of approximately 20-30 atomic percent.
FIG. 1d schematically illustrates the semiconductor device 100 when exposed to an etch ambient 110, in which the mask 103 (FIG. 1c) is removed selectively to the semiconductor materials of the active regions 102A, 102B, wherein it should be understood that the active region 102A may now comprise the silicon/germanium alloy 109. Moreover, during the etch process 110, which may be performed on the basis of hydrofluoric acid, the exposed semiconductor surface areas may also be prepared for forming a sophisticated gate dielectric material having an increased dielectric constant, as explained above.
FIG. 1e schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which a gate dielectric material 161 is formed on the active regions 102A, 102B. For example, the gate dielectric material 161 comprises a first layer 161A, such as a silicon dioxide material, a silicon oxynitride material and the like, above which a further dielectric material 161B is formed, which may include any appropriate material species for increasing the dielectric constant. For this purpose, the layer 161A is typically provided with a reduced thickness of less than one nanometer, and the layer 161B may have a sufficiently high dielectric constant in order to provide the required capacitive coupling, while a total thickness of the dielectric material 161 may reduce the overall gate leakage currents, as is also previously discussed. The gate dielectric material 161 may be formed on the basis of any appropriate process technique, such as deposition techniques in the form of chemical vapor deposition (CVD) and the like. During the deposition of the materials 161A, 161B, it is believed that, in particular, the interface 109S between the dielectric material 161 and the silicon/germanium alloy 109 may have an increased roughness, which is assumed to cause significant threshold voltage variations.
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a gate layer stack 160S is formed above the active regions 102A, 102B and comprises the gate dielectric material 161. Furthermore, a first material system 162 is formed above the active region 102A and may comprise any appropriate conductive materials in order to connect to the gate dielectric material 161 so as to obtain a desired work function. For example, the material system 162 may comprise a titanium nitride material formed on the gate dielectric material 161, followed by a work function adjusting species, such as aluminum, followed by a further titanium nitride material. On the other hand, the material system 163 is formed above the active region 102B so as to connect to the gate dielectric material 161 in order to obtain the desired work function. For example, the material system 163 may comprise a layer of lanthanum material followed by a titanium nitride material. Moreover, an electrode material 164, such as amorphous silicon, polysilicon and the like, in combination with a dielectric cap material 165, such as silicon dioxide, silicon nitride and the like, are provided in the gate layer stack 1605.
The material system 162 may be provided on the basis of any appropriate deposition technique, such as CVD, physical vapor deposition (PVD) and the like. For example, titanium nitride may be sputter deposited in a nitrogen-containing ambient, followed by the sputter deposition of aluminum and the deposition of a titanium nitride material. Thereafter, this layer system may be patterned so as to remove at least the aluminum material from above the active region 102B. Next, the material system 163 may be deposited, followed by the deposition of the material 164 and the cap layer 165. It should be appreciated that further materials may be deposited, such as hard mask materials and the like, as required for the further processing of the device 100.
FIG. 1g schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, a first gate electrode structure 160A is formed on the active region 102A, which includes the threshold adjusting semiconductor alloy 109, while a second gate electrode structure 160B is formed on the active region 102B. The gate electrode structures 160A, 160B may be formed on the basis of any appropriate complex lithography and etch techniques in order to obtain the desired gate length of, for instance, 40 nm and less in sophisticated semiconductor devices. It should be appreciated that the gate length is to be understood as the horizontal extension of the gate electrode structures 160A, 160B, for instance by using the lateral extension of the material systems 162 and 163, respectively.
Thereafter, the further processing may be continued by forming drain and source regions in the active regions 102A, 102B in accordance with any appropriate process strategy.
As previously indicated, in particular, a corresponding transistor including the gate electrode structure 160A may exhibit significant threshold voltage variations over the operational lifetime, which is believed to be caused by the increasing number of trapped interface charges, as explained above. Consequently, reliability of the device 100 over lifetime may not be guaranteed, thereby contributing to a significant yield loss.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.